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MC44818 PLL Tuning Circuit with I2C Bus
The MC44818 is a tuning circuit for TV and VCR tuner applications. It contains, on one chip, all the functions required for PLL control of a VCO. This integrated circuit also contains a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. The MC44818 is a pin compatible drop in replacement for the MC44817, where the only difference is the MC44818 has a fixed divide-by-8 prescaler (cannot be bypassed) and the MC44817 uses the three wire bus. The MC44818 has a programmable 512/1024 reference divider and is manufactured on a single silicon chip using Motorola's high density bipolar process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits). * Complete Single Chip System for MPU Control (I2C Bus). Data and Clock Inputs are 3-Wire Bus Compatible * Divide-by-8 Prescaler Accepts Frequencies up to 1.3 GHz
TV AND VCR PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND I2C BUS
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * *
15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz Reference Divider: Programmable for Division Ratios 512 and 1024. 3-State Phase/Frequency Comparator Operational Amplifier for Direct Tuning Voltage Output (30 V) Four Integrated PNP Band Buffers for 40 mA (VCC1 to 14.4 V) Output Options for the Reference Frequency and the Programmable Divider High Sensitivity Preamplifier Circuit to Detect Phase Lock Fully ESD Protected
16 1
D SUFFIX PLASTIC PACKAGE CASE 751B (SO-16)
MOSAIC is a trademark of Motorola, Inc.
PIN CONNECTIONS
SDA SCL XTAL Amp In VTUN VCC2 33 V Package SO-16 HF In VCC1 5.0 V
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
AS Lock VCC3 12 V B3 B2 B1 B0 Gnd
ORDERING INFORMATION
Device MC44818D Operating Temperature Range TA = -20 to +80C
(Top View)
(c) Motorola, Inc. 1996
Rev 2
MOTOROLA ANALOG IC DEVICE DATA
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MC44818
Representative Block Diagram
Bands Out 30 mA (40 mA at 0 to 80C) VCC1 5.0 V 7 13 12 11 10 VCC3 14 12 V 5 20 k Fout Fref Test Logic DTB1 Gnd 9 B3 B2 B1 B0 Buffers Latches T13 T9, T12, T14 T10, T11 P-On Reset DTB2 POR AS Data Clock 16 1 2 I2C Bus Receiver CL Data RL DTF 4 Shift Register 15 Bit 15 Latches A Osc Latches B 3 XTAL 6 512/1024 Latches Fout Fref 4 2.7 V Operational Amplifier Phase Comp Amp In VTUN VCC2 6
15
Lock
Ref Divider
TDI
HF Input
8
/8 Prescaler
Program Divider 15 Bit
Fout
Latch Control
DTS, EN This device contains 3,204 active transistors.
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Rating Power Supply Voltage (VCC1) Band Buffer "Off" Voltage Band Buffer "On" Current Band Buffer - Short Circuit Duration (0 to VCC3) (Note 2) Operational Amplifier Power Supply Voltage (VCC2) Operational Amplifier Short Circuit Duration (0 to VCC2) Power Supply Voltage (VCC3) Storage Temperature Operating Temperature Range Band Buffer Operation (Note 1) at 50 mA each Buffer All Buffers "On" Simultaneously Operational Amplifier Output Voltage RF Input Level (10 MHz to 1.3 GHz) Pin 7 10-13 10-13 10-13 6 5 14 - - 10-13 5 - Value 6.0 14.4 50 Continuous 40 Continuous 14.4 - 65 to +150 - 20 to +80 10 VCC2 1.5 Unit V V mA - V - V C C sec V Vrms
NOTES: 1. At VCC3 = VCC1 to 14.4 V and TA = - 20 to + 80C. 2. At VCC3 = VCC1 to 14.4 V and TA = - 20 to + 80C one buffer "On" only.
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MOTOROLA ANALOG IC DEVICE DATA
MC44818
ELECTRICAL CHARACTERISTICS (VCC1 = 5.0 V, VCC2 = 33 V, VCC3 = 12 V, TA = 25C, unless otherwise noted.)
Characteristic VCC1 Supply Voltage Range VCC1 Supply Current (VCC1 = 5.0 V) VCC2 Supply Voltage Range VCC2 Supply Current (Output Open) Band Buffer Leakage Current when "Off" at 12 V Band Buffer Saturation Voltage when "On" at 30 mA Band Buffer Saturation Voltage when "On" at 40 mA only for 0 to 80C Data/Clock Current at 0 V Clock Current at 5.0 V Data Current at 5.0 V Acknowledge "Off" Data Saturation Voltage at 15 mA Acknowledge "On" Data/Clock Input Voltage Low Data/Clock Input Voltage High Clock Frequency Range Oscillator Frequency Range Operational Amplifier Internal Reference Voltage Operational Amplifier Input Current DC Open Loop Voltage Gain Gain Bandwidth Product (CL = 1.0 nF) Vout Low, Sinking 50 A Vout High, Sourcing 10 A, VCC2 - Vout Phase Detector Current in the High Impedance State Charge Pump High Current of Phase Comparator Charge Pump Low Current of Phase Comparator VCC3 Supply Voltage Range VCC3 Supply Current All Buffers "Off" One Buffer "On" when Open One Buffer "On" at 40 mA Pin 7 7 6 6 10-13 10-13 10-13 1, 2 2 1 1 1, 2 1, 2 2 3 - 4 - - 5 5 4 4 4 14 14 - - - 0.2 8.0 48 0.5 13 53 Min 4.5 - 25 - - - - -10 0 0 - - 3.0 - 3.15 2.0 -15 100 0.3 - - -15 30 10 VCC1 Typ 5.0 37 - 1.5 0.01 0.15 0.2 - - - - - - - 3.2 2.75 0 250 - 0.2 0.2 0 50 15 - Max 5.5 50 37 2.3 1.0 0.3 0.5 0 1.0 1.0 1.0 1.5 - 100 4.05 3.2 15 - - 0.4 0.5 15 85 30 14.4 Unit V mA V mA A V V A A A V V V kHz MHz V nA V/V MHz V V nA A A V mA
Data Format and Bus Receiver The circuit receives the information for tuning and control via the I2C bus. The incoming information, consisting of a chip address byte followed by two or four data bytes, is treated in the I2C bus receiver. The definition of the permissible bus protocol is shown below: 1_STA 2_STA 3_STA CA CA CA CO FM CO BA FL BA STO STO FM FL
STO
4_STA CA FM FL CO BA STO STA = Start Condition STO = Stop Condition CA = Chip Address Byte CO = Data Byte for Control Information BA = Band Information FM = Data Byte for Frequency Information FL = Data Byte for Frequency Information
Figure 1. Complete Data Transfer Process
SDA
SCL 1-7 S STA ADDRESS CA R/W ACK DATA ACK DATA ACK 8 9 1-7 8 9 1-7 8 9 P STO
MOTOROLA ANALOG IC DEVICE DATA
3
MC44818
Figure 2 shows the five bytes of information that are needed for circuit operation: there is the chip address, two bytes of control and band information and two bytes of frequency information. After the chip address, two or four data bytes may be received: if three data bytes are received the third data byte is ignored. If five or more data bytes are received the fifth and following data bytes are ignored and the last acknowledge pulse is sent at the end of the fourth data byte. The first and the third data bytes contain a function bit which allows the IC to distinguish between frequency information and control plus band information. Frequency information is preceeded by a Logic "0". If the function bit is Logic "1" the two following bytes contain control and band information. The first data byte, shifted after the chip address, may be byte CO or byte FM. The two permissible bus protocols with five bytes are shown in Figure 2.
Figure 2. Definition of Bytes
CA_Chip Address 1 1 0 0 0 0/1 0/1 0 ACK
CO_Information BA_Band Information
FM_Frequency Information FL_Frequency Information CA_Chip Address
FM_Frequency Information FL_Frequency Information
CO_Information BA_Band Information
Chip Address The chip address is programmable by Pin 16 (AS - Address Select).
AS - Pin 16 Gnd to 0.1 VCC1 Open or 0.2 VCC1 to 0.3 VCC1 0.4 VCC1 to 0.7 VCC1 0.8 VCC1 to 1.1 VCC1 Address (HEX.) C0 C2 C4 C6
Bits B0, B1, B2, B3: Control the Band Buffers
B0, B1, B2, B3 = 0 B0, B1, B2, B3 = 1 Buffer "Off" Buffer "On"
Figure 3. Equivalent Circuit of the Integrated Band Buffers
VCC3 12 V 25 V Protection Gnd IB ISUB 30 mA (40 mA at 0 to 80C)
"On"/"Off" Out B0...B3
NOTE: IB + ISUB = 8.0 mA Typical, 13 mA Max
IB = Base Current ISUB = Substrate Current of PNP
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EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE
1 T14 X T13 X T12 X T11 B3 T10 B2 T9 T8 ACK ACK X B1 B0 0 N14 N6 1 N13 N5 0 N12 N4 0 N11 N3 0 N10 N2 N9 N1 N8 N0 0 ACK ACK ACK N7 1
EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE
0 N14 N6 N13 N5 N12 N4 N11 N3 N10 N2 N9 N1 N8 N0 ACK ACK N7 1 T14 X T13 X T12 X T11 B3 T10 B2 T9 T8 ACK ACK X B1 B0
0/1
0/1
Bit T8: Controls the Output of the Operational Amplifier
T8 = 0 T8 = 1 Normal Operation Operational Amplifier Active Output State of Operational Amplifier Switched "Off", Output Pulls High Through 20 k Internal Pull-Up Resistor
Bits T9, T12: Control the Phase Comparator
T9 1 1 0 0 T12 0 1 0 1 Function Normal Operation High Impedance Upper Source "On" Only Lower Source "On" Only
Bits T10, T11: Control the Reference Ratio
T10 0 0 1 1 T11 0 1 0 1 512 1024 1024 512 Division Ratio
Bit T13: Switches the Internal Signals Fref and FBY2 to Bit T13: the Band Buffer Outputs (Test)
T13 = 0 T13 = 1 Normal Operation Test Mode Fref Output at B2 (Pin 12) FBY2 Output at B3 (Pin 13)
Bits B2 and B3 have to be "On", B2 = B3 = 1 in the test mode. Fref is the reference frequency. FBY2 is the output frequency of the programmable divider, divided by two.
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Bit T14: Controls the Charge Pump Current of the Bit T14: Phase Comparator
T14 = 0 T13 = 1 Pump Current 15 A Typical Pump Current 50 A Typical
Lock Detector The lock detector output is low in lock. The output goes immediately high when an unlock condition is detected. The output goes low again when the loop is in lock during a complete period of the reference frequency. Figure 4. Equivalent Circuit of the Lock Output
VCC1 5.0 V 200 A Typical 2.0 k Lock 100 k 25 V Protection
The Programmable Divider The programmable divider is a presettable down counter. When it has counted to zero it takes its required division ratio out of the latches B. Latches B are loaded from latches A by means of signal TDI which is synchronous to the programmable divider output signal. Since latches A receive the data asynchronously with the programmable divider; this double latch scheme is needed to assure correct data transfer to the counter. The division ratio definition is given by: N = 16384 x N14 + 8192 x N13 + ... + 4 x N2 + 2 x N1 + N0 Maximum Ratio 32767 Minimum Ratio 17 N0 ... N14 are the different bits for frequency information. At power "on" the whole bus receiver is reset and the programmable divider is set to a counting ratio of N = 256 or higher. The Prescaler The prescaler has a preamplifier which guarantees high input sensitivity. The Phase Comparator The phase comparator is phase and frequency sensitive and has very low output leakage current in the high impedance state.
The Operational Amplifier The operational amplifier is designed for very low noise, low input bias current and high power supply rejection. The positive input is biased internally. The operational amplifier needs 28.5 V supply (VCC2) as minimum voltage for a guaranteed maximum tuning voltage of 28 V. Figure NO TAG shows a possible filter arrangement. The component values depend very much on the application (tuner characteristic, reference frequency, etc.). The Oscillator The oscillator uses a 3.2 to 4.0 MHz crystal tied to ground in series with a capacitor. The crystal operates in the series resonance mode. The voltage at Pin 3 has low amplitude and low harmonic distortion.
Figure 5. Typical Tuner Application
IF UHF VHF B III 5.0 V 7 Mixer B. P. Filter 1.0 nF Fosc Gnd 9 6 VTUN AGC
NOTES: 1. On some layouts the 100 resistor will not be required. 2. C2 = 330 pF minimum is required for stability.
External Switching
13 B3
12 B2
11 B1
10 B0 Bus Rec Program Divider
14 12 V VCC3 2 1 16 Osc & 3 Ref Div Phase Comp 15 Lock SCL SDA AS
Antenna Filter
MC44818
8 /8 Pres
12 pF 3.2/4.0 MHz
Oscillator
2.7 V 5 (Note 1) 47 k 4
330 p (Note 2) 33 V
47 nF 22 nF
MOTOROLA ANALOG IC DEVICE DATA
5
MC44818
Figure 6. HF Sensitivity Test Circuit
Bus Controller
HF Generator HF Out Gnd 50 Cable 50 1.0 nF 4.7 k 4.7 k 390 390 In Frequency Counter
Device is in test mode. B2, B3 are "On" and B0, B1 are "Off". Sensitivity is level of HF generator on 50 load (without Pin 8 loading).
HF CHARACTERISTICS (See Figure NO TAG) Characteristic DC Bias Input Voltage Range 80-150 MHz 150-600 MHz 600-950 MHz 950-1300 MHz Pin 8 8 8 8 8 Min - 10 5.0 10 50 Typ 1.6 - - - - Max - 315 315 315 315 Unit V mVrms
1 1.0 GHz
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CCCCCCCCCCCC CCCCCCCCCCCC CCCCCCCCCCCC
1 2 VCC1 7 HF 8 Gnd 9 B0 10 -j 0 +j 0.5 0.5 ZO = 50 1.3 GHz 1 2 2 500 MHz 50 MHz
Bus
VCC3 14
MC44818 B1 11 B2 12 B3 13
Figure 7. Typical HF Input Impedance
0.5
1
2
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Figure 8. Pin Circuit Schematic
VCC1 132 k SDA 1 Data input (I2C bus) 50 96 k 1/2 VCC1 96 k ACK VCC1 132 k 500 SCL 2 Clock input (supplied by a microprocessor via I2C bus) 96 k 1/2 VCC1 96 k
VCC1 150 k 500 16 AS Address Select (I2C bus)
20 V
50 k
20 V
VCC1
2.0 k 15 LOCK Lock detector output 100 k 20 V
20 V
XTAL 3 Crystal oscillator (3.2 MHz or 4.0 MHz)
100 5.0 V "On"/"Off" 20 V
20 V
14 VCC3 Positive supply for integrated band buffers (12 V)
13 B3
2.0 k AMP IN 4 Negative input of operation amplifier and charge pump output 20 V
10 k 20 V "On"/"Off" 20 k
12 B2
100 VTUN 5 Operational amplifier output which provides the tuning voltage 20 V 20 V 20 V "On"/"Off" VCC2 6 Operational amplifier positive supply (33 V) 20 V 20 V 11 B1
Band buffer outputs can drive up to 30 mA (40 mA at 0 to 80C)
VCC1 7 Positive supply of the circuit (5.0 V)
5.0 V 5.0 V "On"/"Off" 18 k 2.0 k 1.2 ... 1.8 V
20 V
10 B0
HF IN 8 HF input from local oscillator
2.0 k 9 GND Circuit Ground
MOTOROLA ANALOG IC DEVICE DATA
7
MC44818
OUTLINE DIMENSIONS
D SUFFIX PLASTIC PACKAGE CASE 751B-05 (SO-16) ISSUE J -A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.229 0.244 0.010 0.019
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-B-
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
K C -T-
SEATING PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
TB
S
A
S
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*MC44818/D*
MOTOROLA ANALOG IC DEVICE DATA MC44818/D

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